Example description

  
Interrupts

This example application demonstrates the interrupt preemption and
tail-chaining capabilities of Cortex-M3 microprocessor and NVIC.  Nested
interrupts are synthesized when the interrupts have the same priority,
increasing priorities, and decreasing priorities.  With increasing
priorities, preemption will occur; in the other two cases tail-chaining
will occur.  The currently pending interrupts and the currently executing
interrupt will be displayed on the OLED; GPIO pins B0, B1 and B2 will be
asserted upon interrupt handler entry and de-asserted before interrupt
handler exit so that the off-to-on time can be observed with a scope or
logic analyzer to see the speed of tail-chaining (for the two cases where
tail-chaining is occurring).

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Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
Software License Agreement

Luminary Micro, Inc. (LMI) is supplying this software for use solely and
exclusively on LMI's microcontroller products.

The software is owned by LMI and/or its suppliers, and is protected under
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OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

This is part of revision 4652 of the EK-LM3S6965 Firmware Package.